1. Field of the Invention
The present disclosure relates to electronic-design-automation (EDA) techniques. More specifically, the present disclosure relates to a technique for sub-module physical refinement in the absence of specific physical hierarchy.
2. Related Art
As semiconductor technology is scaled to ever smaller dimensions, there are commensurate increases in the complexity of digital circuit designs. For example, smaller dimensions typically result in digital circuit designs having an increased number of logic gates and time domains. Moreover, this increase in complexity typically results in a significant increase in the time and cost needed to design and implement digital circuits.
Digital circuit design fundamentally has two components: abstraction of the functionality of the circuit via computer models, and the actual physical rendering and implementation of the design. The development of any given design progresses from one phase to the next; from functional abstraction via computer modeling to physical rendering. In this progression, there becomes a point where the lines between the two are blurred. Aspects of the physical implementation have to be accounted for in the functional computer modeling; and functional aspects of the circuit have to be accounted for in the physical implementation.
In addition, given today's designs that can be very large and complex, there is a need to break the larger design into smaller sub-circuits that are more easily handled. These sub-circuits are then put together to accomplish the larger design. This fracturing and reconstitution of the larger design applies in both the computer modeling of the functionality and the physical implementation or rendering.
As the number of sub-circuits increases so does the complexity of the process of fracturing and reconstitution. Thus, it is desirable to limit the number of sub-circuits. Accordingly, the sub-circuits themselves can be quite complex.
At the point where the lines between the two phases of the design process blur, the current state of the art requires that there be a one-to-one correspondence between the sub-circuits of the functional modeling and the sub-circuits of the physical implementation.
This need for one-to-one correspondence often causes difficulties and inefficiencies for the designer. For example, the designer may need to change or successively refine a small portion of the sub-circuit in the functional model, but cannot do so because there is no corresponding physical sub-circuit for the portion he desires to change. Accordingly, the designer working on the computer modeling of the functionality is forced to rebuild the entire sub-circuit resulting in inefficiencies of build time and the possible introduction of additional problems and errors. Circuit designers need a way to rebuild and physically refine only a desired portion of a given sub-circuit.
Hence, there is a need for an EDA technique to provide this capability. That is, there is a need to be able to perform physical synthesis on a sub-module of a circuit design for which no physical hierarchy is defined that eliminates the need to resynthesize the larger circuit and thereby improve efficiency while avoiding the possible introduction of errors and creation of other problems.